The present invention relates to placement and routing of an electronic circuit, and more particularly to a knowledge-based analog layout generation method and system.
Modern system-on-chip (SoC) design often contains both digital and analog circuits. The digital circuit design has been extensively assisted by modern design automation tools, while the analog counterpart is still a manual, time-consuming, and error-prone task because the performance specification of modern analog circuits are becoming increasingly stringent.
Many placement-and-routing methods have been proposed to automatically generate analog layouts while considering various analog layout constraints, such as symmetry, regularity, common centroid, thermal gradient, monotonic current paths, and other general placement constraints. Although these layout constraints are designed to minimize the impact from layout-induced parasitics, the resulting layouts are sometimes unacceptable because manual layouts contain much more experts' knowledge, and designers may have their own layout preferences, which cannot simply be expressed by those layout constraints.